1 research outputs found
Digital PLL for ISM applications
In modern transceivers, a low power PLL is a key block. It is known that with the
evolution of technology, lower power and high performance circuitry is a challenging
demand.
In this thesis, a low power PLL is developed in order not to exceed 2mW of total power
consumption. It is composed by small area blocks which is one of the main demands.
The blocks that compose the PLL are widely abridged and the final solution is shown,
showing why it is employed. The VCO block is a Current-Starved Ring Oscillator with
a frequency range from 400MHz to 1.5GHz, with a 300μW to approximately 660μW
power consumption. The divider is composed by six TSPC D Flip-Flop in series, forming
a divide-by-64 divider. The Phase-Detector is a Dual D Flip-Flop detector with a charge
pump. The PLL has less than a 2us lock time and presents a output oscillation of 1GHz,
as expected. It also has a total power consumption of 1.3mW, therefore fulfilling all the
specifications.
The main contributions of this thesis are that this PLL can be applied in ISM applications
due to its covering frequency range and low cost 130nm CMOS technology